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Altera has announced the Nios II C-to-Hardware Acceleration (C2H) Compiler, a productivity tool for developers of Nios II-based systems that substantially increases the performance of their embedded software. As the number of embedded designs using FPGAs increases, the availability of the Nios II C2H Compiler is targeted at providing developers of embedded systems with the tools they need to be productive and successful. As part of the Nios II C2H Compiler offering, Altera is also providing third-party tools vendors with access to its system-level infrastructure, including the Quartus II SOPC Builder tool, to foster development of a wide range of Electronic System Level (ESL) design tools. The Nios II C2H Compiler leverages Altera’s system-level infrastructure to deliver substantial performance improvement across a broad range of applications. The new tool automatically converts performance-critical C language subroutines into hardware accelerators, and integrates them into FPGA-based Nios II subsystems, reducing development time from weeks to minutes. The Nios II C2H Compiler is currently shipping to beta customers and will be available for general release in May 2006. It will be delivered as an integrated plug-in to the Nios II IDE.